/* Copyright 2018 ETH Zurich and University of Bologna.
 * Copyright and related rights are licensed under the Solderpad Hardware
 * License, Version 0.51 (the "License"); you may not use this file except in
 * compliance with the License.  You may obtain a copy of the License at
 * http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
 * or agreed to in writing, software, hardware and materials distributed under
 * this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
 * CONDITIONS OF ANY KIND, either express or implied. See the License for the
 * specific language governing permissions and limitations under the License.
 *
 * File: $filename.v
 *
 * Description: Auto-generated bootrom
 */

// Auto-generated code
module rom (
   input  logic         clk_i,
   input  logic         req_i,
   input  logic [63:0]  addr_i,
   output logic [63:0]  rdata_o
);
    localparam int RomSize = 30;

    const logic [RomSize-1:0][63:0] mem = {
        64'h00000000_00000000,
        64'h00000000_0a343676,
        64'h63736972_20646c72,
        64'h6f77206f_6c6c6568,
        64'h00008067_00000513,
        64'h00a72023_0005051b,
        64'hfe078ce3_0207f793,
        64'h01472783_40000737,
        64'h00008067_00e7a623,
        64'h00300713_00e7a423,
        64'h0c600713_0007a023,
        64'h0007a223_00e7a623,
        64'h08000713_400007b7,
        64'h0000006f_0000006b,
        64'h00050513_f99ff0ef,
        64'h07850513_00000517,
        64'h01c000ef_00113423,
        64'hff010113_0500006f,
        64'h00008067_02010113,
        64'h00000513_00813483,
        64'h01013403_01813083,
        64'hfe0490e3_fff4849b,
        64'hfe051ae3_00044503,
        64'h02c000ef_00140413,
        64'h06800513_0ac40413,
        64'h00000417_06400493,
        64'h00813823_00113c23,
        64'h00913423_fe010113,
        64'h058000ef_ffc10113,
        64'h3e008117_00000413
    };

    logic [$clog2(RomSize)-1:0] addr_q;

    always_ff @(posedge clk_i) begin
        if (req_i) begin
            addr_q <= addr_i[$clog2(RomSize)-1+3:3];
        end
    end

    // this prevents spurious Xes from propagating into
    // the speculative fetch stage of the core
    assign rdata_o = (addr_q < RomSize) ? mem[addr_q] : '0;
endmodule
